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   &#160;<span id="projectnumber">Version 1.1.4</span>
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<p>Functions to access the Cortex-A core registers.  
<a href="#details">More...</a></p>
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Content</h2></td></tr>
<tr class="memitem:group__CMSIS__ACTLR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></td></tr>
<tr class="memdesc:group__CMSIS__ACTLR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CBPM"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html">Cache and branch predictor maintenance operations</a></td></tr>
<tr class="memdesc:group__CMSIS__CBPM"><td class="mdescLeft">&#160;</td><td class="mdescRight">This section describes the cache and branch predictor maintenance operations. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CBAR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBAR.html">Configuration Base Address Register (CBAR)</a></td></tr>
<tr class="memdesc:group__CMSIS__CBAR"><td class="mdescLeft">&#160;</td><td class="mdescRight">Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CPACR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR.html">Coprocessor Access Control Register (CPACR)</a></td></tr>
<tr class="memdesc:group__CMSIS__CPACR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The CPACR controls access to coprocessors CP0 to CP13. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CPSR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></td></tr>
<tr class="memdesc:group__CMSIS__CPSR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Current Program Status Register (CPSR) holds processor status and control information. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__DFSR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR.html">Data Fault Status Register (DFSR)</a></td></tr>
<tr class="memdesc:group__CMSIS__DFSR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The DFSR holds status information about the last data fault. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__DACR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR.html">Domain Access Control Register (DACR)</a></td></tr>
<tr class="memdesc:group__CMSIS__DACR"><td class="mdescLeft">&#160;</td><td class="mdescRight">DACR defines the access permission for each of the sixteen memory domains. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__FPEXC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPEXC.html">Floating-Point Exception Control register (FPEXC)</a></td></tr>
<tr class="memdesc:group__CMSIS__FPEXC"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__FPSCR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPSCR.html">Floating-point Status and Control Register (FPSCR)</a></td></tr>
<tr class="memdesc:group__CMSIS__FPSCR"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides floating-point system status information and control. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__IFSR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR.html">Instruction Fault Status Register (IFSR)</a></td></tr>
<tr class="memdesc:group__CMSIS__IFSR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IFSR holds status information about the last instruction fault. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__ISR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR.html">Interrupt Status Register (ISR)</a></td></tr>
<tr class="memdesc:group__CMSIS__ISR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The ISR shows whether an IRQ, FIQ, or external abort is pending. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__MPIDR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MPIDR.html">Multiprocessor Affinity Register (MPIDR)</a></td></tr>
<tr class="memdesc:group__CMSIS__MPIDR"><td class="mdescLeft">&#160;</td><td class="mdescRight">In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CNTFRQ"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTFRQ.html">Counter Frequency register (CNTFRQ)</a></td></tr>
<tr class="memdesc:group__CMSIS__CNTFRQ"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates the clock frequency of the system counter. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CNTP__CTL"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CTL.html">PL1 Physical Timer Control register (CNTP_CTL)</a></td></tr>
<tr class="memdesc:group__CMSIS__CNTP__CTL"><td class="mdescLeft">&#160;</td><td class="mdescRight">The control register for the physical timer. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CNTP__CVAL"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CVAL.html">PL1 Physical Timer Compare Value register (CNTP_CVAL)</a></td></tr>
<tr class="memdesc:group__CMSIS__CNTP__CVAL"><td class="mdescLeft">&#160;</td><td class="mdescRight">Holds the 64-bit compare value for the PL1 physical timer. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CNTP__TVAL"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__TVAL.html">PL1 Physical Timer Value register (CNTP_TVAL)</a></td></tr>
<tr class="memdesc:group__CMSIS__CNTP__TVAL"><td class="mdescLeft">&#160;</td><td class="mdescRight">Holds the timer value for the PL1 physical timer. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__CNTPCT"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTPCT.html">PL1 Physical Count register (CNTPCT)</a></td></tr>
<tr class="memdesc:group__CMSIS__CNTPCT"><td class="mdescLeft">&#160;</td><td class="mdescRight">Holds the 64-bit physical count value. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__SP"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SP.html">Stack Pointer (SP/R13)</a></td></tr>
<tr class="memdesc:group__CMSIS__SP"><td class="mdescLeft">&#160;</td><td class="mdescRight">The processor uses SP as a pointer to the active stack. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__SCTLR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></td></tr>
<tr class="memdesc:group__CMSIS__SCTLR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The SCTLR provides the top level control of the system, including its memory system. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__TLB"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TLB.html">TLB maintenance operations</a></td></tr>
<tr class="memdesc:group__CMSIS__TLB"><td class="mdescLeft">&#160;</td><td class="mdescRight">This section describes the TLB operations that are implemented on all Armv7-A implementations. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__TTBR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html">Translation Table Base Registers (TTBR0/TTBR1)</a></td></tr>
<tr class="memdesc:group__CMSIS__TTBR"><td class="mdescLeft">&#160;</td><td class="mdescRight">TTBRn holds the base address of translation table n, and information about the memory it occupies. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__VBAR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__VBAR.html">Vector Base Address Register (VBAR)</a></td></tr>
<tr class="memdesc:group__CMSIS__VBAR"><td class="mdescLeft">&#160;</td><td class="mdescRight">When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__CMSIS__MVBAR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MVBAR.html">Monitor Vector Base Address Register (MVBAR)</a></td></tr>
<tr class="memdesc:group__CMSIS__MVBAR"><td class="mdescLeft">&#160;</td><td class="mdescRight">The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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